1. Field of the Invention
The present invention relates to a loop filter, and more particularly to a loop filter structure with a high speed and a small area.
2. Description of the Related Art
Generally, sequencing is essential for electronic or computer systems. Accordingly, periodic clock signals and reference clock signals must be precisely synchronized. The phase-lock loop (PLL) is a widely used circuit which can precisely synchronize the frequency of output signals and frequency of input signals. The PLL usually is applied in a frequency synthesizer, multiplier, divider, single or multiple clock signal generator, clock signal recover circuit, and wireless communication apparatus.
FIG. 1 is a circuit block diagram showing a conventional phase-lock loop. Referring to FIG. 1, the output terminal of the oscillator 101, such as a quartz oscillator, is coupled to the frequency divider 103, and to the phase-detection circuit 105 through the phase divider 103. The phase-detection circuit 105 operates the loop filter 109 through the charge pump circuit 107. The output terminal of the loop filter 109 is coupled to the output terminal OUT of the phase-lock loop, and to the voltage-control oscillator 111. The voltage oscillator 111, according to the loop filter 109, transmits the output to the frequency divider 113, and the output of the frequency divider 113 is fed back to the input of the phase-detection circuit 105.
The loop filter 109 shown in FIG. 1 is a second-order loop filter. In detail, the order of the loop filter is determined by the number of its capacitors. The loop filter 109 comprises the capacitors Cp and Cz, and the resistor Rz. Wherein, the capacitor Cp is called a pole capacitor, which is used to provide a pole point in the system. One terminal of the capacitor Cp is coupled between the input terminal and the output terminal of the loop filter 109, and another terminal is grounded. In addition, the resistor Rz and the capacitor Cz provide a zero point in this system. Wherein, one terminal of the resistor Rz is coupled between the input terminal and the output terminal of the loop filter 109, and another terminal is grounded through the capacitor Cz.
Generally, the zero point is generated before the pole point. Accordingly, the capacitance of the capacitor Cz should be much larger than that of the capacitor Cp. As a result, the capacitor Cz has a great area. In order to reduce the capacitance of the capacitor Cz, and to generate the zero point before the pole point, a related technique is developed.
FIG. 2 is a circuit block diagram showing an improved phase-lock loop. Referring to FIG. 2, the phase-lock loop is the phase-lock loop of FIG. 1 with additional charge pump circuit 201. Wherein, the operation of the charge pump circuit 201 is contrary to that of the charge pump circuit 107. That is, when the charge pump circuit 107 charges the loop filter 109, the charge pump circuit 201 discharges the capacitor Cz, and vice versa. Accordingly, the current flowing through the capacitor Cz is reduced, and the capacitance of the capacitor Cz is reduced, too.
The phase-lock loop of FIG. 2, however, has a disadvantage. The additional charge pump circuit 201 in the phase-lock loop of FIG. 2 can reduce the capacitance of the capacitor Cz, and so reduce the area of the capacitor Cz, but the charge pump circuit 201 is added and so the area is increased. Moreover, there is mismatch issue between the charge pump circuits 107 and 201.